Computer networks may facilitate communication by establishing links between nodes (e.g. computer, server, and stand-alone peripheral) of a network. These links may be physical or logical paths from a sender of a piece of information to its receiver. Each node of a network depends upon these links to communicate with other nodes. The information may be communicated in the form of data blocks, commonly referred to as frames.
Due to the growing number of nodes in networks, it is often impractical to directly connect every pair of sender-receiver nodes with a direct link. Consequently, many networks include switches for routing frames through shared intermediate links. Each switch may include multiple ports through which frames enter and exit the switch on network links. The switch is responsible for routing frames onto links that transport the frames closer to their destination. Each switch may be simultaneously routing frames from multiple nodes through multiple links of the network.
High bandwidth switches may utilize 256 or more ports to handle large amounts of data from numerous connected switches. Frames may be received from a connected switch through an external switch port and then placed into switch memory. In order to ensure coherency of the data stored in switch memory, only one port may have access to any given memory unit at any given time. Since multiple ports may need to access identical memory units to transfer a common frame from switch memory, memory delays may occur. These delays may increase the time it takes for data to travel from its source to its destination in the network, referred to as latency. A memory architecture that prevents such delays would be desirable.